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advance information 1-mbit (128k x 8) nv sram with real-time clock cy14b101k cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06401 rev. *a revised february 22, 2006 features ? data integrity of cypress nvsram combined with full-features real-time clock ? watchdog timer ? clock alarm with programmable interrupts ? capacitor or battery backup for rtc ? 25 ns, 35 ns, and 45 ns access times ? ?hands-off? automatic store on power down with only a small capacitor ? store to quantumtrap? initiated by software, device pin, or on power down ? recall to sram initiated by software or on power up ? unlimited read, write and recall cycles ? high-reliability ? endurance to 1 million cycles ? data retention: 100 years ? 5 ma typical i cc at 200-ns cycle time ? single 3v operation +20%, -10% ? ssop package (r ohs compliant) functional description the cypress cy14b101k combines a 1-mbit nonvolatile static ram with a full-featured real-time clock in a monolithic integrated circuit. the embedded nonvolatile elements incor- porate quantumtrap ? technology producing the world?s most reliable nonvolatile memory. the sram can be read and written an unlimited number of times, while independent, nonvolatile data resides in the nonvolatile elements. the real-time clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscil- lator. the alarm function is programmable for one-time alarms or periodic seconds, minutes, hours, or days. there is also a programmable watchdog timer for process control. logic block diagram oe ce we
advance information cy14b101k document #: 001-06401 rev. *a page 2 of 23 pin configurations pin definitions pin name i/o type description a 0 ?a 16 input address inputs used to select one of the 131,072 bytes of the nvsram . dq0 - dq7 input/output bidirectional data i/o lines. used as input or output lines depending on operation nc no connect no connects . this pin is not connected to the die we input write enable input, active low . when selected low, enables data on the i/o pins to be written to the address location latched by the falling edge of ce . ce input chip enable input, active low . when low, selects the chip. when high, deselects the chip. oe input output enable, active low . the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the i/o pins to tri-state. x 1 output crystal connection , drives crystal on start-up. x 2 input crystal connection for 32.768-khz crystal. v rtccap power supply capacitor-supplied backup rtc supply voltage . (left unconnected if v rtcbat is used) v rtcbat power supply battery-supplied backup rtc supply voltage . (left unconnected if v rtccap is used) int output interrupt output . can be programmed to respond to the clock alarm, the watchdog timer and the power monitor. programmable to either ac tive high (push/pull) or low (open-drain) v ss ground ground for the device . should be connected to ground of the system. v cc power supply power supply inputs to the device . hsb input/output hardware store busy . when low this output indicates a hardware store is in progress. when pulled low external to the chip it will initiate a nonvolatile store operation. a weak internal pull-up resistor keeps this pin high if not connected. (connection optional) v cap power supply autostore? capacitor. supplies power to nvsram during power loss to store data from sram to nonvolatile elements. a 16 nc dq7 dq6 dq5 nc dq4 v cc dq3 dq2 dq1 dq0 v ss a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 nc hsb we nc int a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 48-ssop top view (not to scale) oe ce v cc v ss v cap nc v rtcbat x 1 x 2 nc nc nc nc v rtccap
advance information cy14b101k document #: 001-06401 rev. *a page 3 of 23 device operation the cy14b101k nvsram is made up of two functional components paired in the same physical cell. these are a sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram can be transferred to the nonvolatile cell (the store operation), or from the nonvolatile cell to sram (the recall operation). this unique architecture allows all cells to be stored and recalled in parallel. during the store and recall operations sram read and write operations are inhibited. the cy14b101k supports unlimited reads and writes just like a typical sram. in addition, it provides unlimited recall operations from the nonvolatile cells and up to 1 million store operations. sram read the cy14b101k performs a read cycle whenever ce and oe are low while we and hsb are high. the address specified on pins a 0-16 determines which of the 131,072 data bytes will be accessed. when the read is initiated by an address transition, the outputs will be valid after a delay of t aa (read cycle #1). if the read is initiated by ce or oe , the outputs will be valid at t ace or at t doe , whichever is later (read cycle #2). the data outputs will repeatedly respond to address changes within the t aa access time without the need for transitions on any control input pins, and will remain valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed whenever ce and we are low and hsb is high. the address inputs must be stable prior to entering the write cycle and must remain stable until either ce or we goes high at the end of the cycle. the data on the common i/o pins dq 0?7 will be written into the memory if it is valid t sd before the end of a we controlled write or before the end of an ce -controlled write. it is recommended that oe be kept high during the entire write cycle to avoid data bus contention on common i/o lines. if oe is left low, internal circuitry will turn off the output buffers t hzwe after we goes low. autostore? operation the cy14b101k stores data to nvsram using one of three storage operations. these th ree operations are hardware store, activated by hsb , software store, activated by an address sequence, and autostore, on device power-down. autostore operation is a un ique feature of quantumtrap technology and is enabled by default on the cy14b101k. during normal operation, the device will draw current from v cc to charge a capacitor connected to the v cap pin. this stored charge will be used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part will automatically disconnect the v cap pin from v cc . a store operation will be initiated with power provided by the v cap capacitor. figure 1 shows the proper connection of the storage capacitor (v cap ) for automatic store operation. refer to the dc charac- teristics table for the size of v cap . the voltage on the v cap pin is driven to 5v by a charge pump internal to the chip. a pull-up should be placed on we to hold it inactive during power-up. to reduce unnecessary nonvolatile stores, autostore and hardware store operations will be ignored unless at least one write operation has taken place since the most recent store or recall cycle. so ftware initiated store cycles are performed regardless of whether a write operation has taken place. the hsb signal can be monitored by the system to detect an autostore cycle is in progress. hardware store (hsb ) operation the cy14b101k provides the hsb pin for controlling and acknowledging the store operations. the hsb pin can be used to request a hardware store cycle. when the hsb pin is driven low, the cy14b101k will conditionally initiate a store operation after t delay . an actual store cycle will only begin if a write to the sram took place since the last store or recall cycle. the hsb pin also acts as an open drain driver that is internally driven low to indicate a busy condition while the store (initiated by any means) is in progress. sram read and write operations that are in progress when hsb is driven low by any means are given time to complete before the store operation is initiated. after hsb goes low, the cy14b101k will c ontinue sram operations for t delay . during t delay , multiple sram read operations may take place. if a write is in progress when hsb is pulled low it will be allowed a time, t delay , to complete. however, any sram write cycles requested after hsb goes low will be inhibited until hsb returns high. during any store operation, regardless of how it was initiated, the cy14b101k wi ll continue to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store operation the cy14b101k will remain disabled until the hsb pin returns high. if hsb is not used, it should be left unconnected. hardware recall (power-up) during power-up, or after any low-power condition (v cc < v switch ), an internal recall request will be latched. when v cc once again exceeds the sense voltage of v switch , a figure 1. autostore tm mode we
advance information cy14b101k document #: 001-06401 rev. *a page 4 of 23 recall cycle will automatically be initiated and will take t hrecall to complete. software store data can be transferred from the sram to the nonvolatile memory by a software address sequence. the cy14b101k software store cycle is init iated by executing sequential ce -controlled read cycles from si x specific address locations in exact order. during the store cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. once a store cycle is initiated, further i nput and output are disabled until the cycle is completed. because a sequence of reads from specific addresses is used for store initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence will be aborted and no store or recall will take place. to initiate the software store cycle, the following read sequence must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8fc0 initiate store cycle the software sequence may be clocked with ce -controlled reads or oe -controlled reads. once the sixth address in the sequence has been entered, the store cycle will commence and the chip will be dis abled. it is important that read cycles and not write cycl es be used in the sequence, although it is not necessary that oe be low for the sequence to be valid. after the t store cycle time has been fulfilled, the sram will again be activated for read and write operation. software recall data can be transferred from the nonvolatile memory to the sram by a software address sequence. a software recall cycle is initiated with a sequence of read operations in a manner similar to the software store initiation. to initiate the recall cycle, the following sequence of ce -controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4c63 initiate recall cycle internally, recall is a two-step procedure. first, the sram data is cleared, and second, the nonvolatile information is transferred into the sram cells. after the t recall cycle time the sram will once again be ready for read and write operations.the recall operation in no way alters the data in the non-volatile elements. preventing autostore the autostore function can be disabled by initiating an autostore disable sequence. a sequence of read operations is performed in a manner similar to the software store initi- ation. to initiate the autostore disable sequence, the following sequence of ce -controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8b45 autostore disable the autostore can be re-enabled by initiating an autostore enable sequence. a sequence of read operations is performed in a manner similar to the software recall initi- ation. to initiate the autostore enable sequence, the following sequence of ce -controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4b46 autostore enable if the autostore function is disabled or re-enabled a manual store operation (hardware or software) needs to be issued to save the autostore state through subsequent power-down cycles. the part comes from the factory with autostore enabled. data protection the cy14b101k protects data from corruption during low-voltage conditions by inhibiting all externally initiated store and write operations. the low voltage condition is detected when v cc < v switch . if the cy14b101k is in a write mode (both ce and we low) at power-up, after a recall, or after a store, the write will be inhibited until a negative transition on ce or we is detected. this protects against inadvertent writes during power-up or brown-out conditions. noise considerations the cy14b101k is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1 f connected between v cc and v ss , using leads and traces that are as short as possible. as with all high-speed cmos ics, careful routing of power, ground and signals will reduce circuit noise.
advance information cy14b101k document #: 001-06401 rev. *a page 5 of 23 low average active power cmos technology provides the cy14b101k, the benefit of drawing significantly less curren t when it is cycled at times longer than 50 ns. figure 2 shows the relationship between i cc and read/write cycle time. worst-case current consumption is shown for commercial temperature range, v cc = 3.6v, and chip enable at maximum frequency. only standby current is drawn when the chip is disabled. the overall average current drawn by the cy14b101k depends on the following items: 1. the duty cycle of chip enable. 2. the overall cycle rate for accesses. 3. the ratio of reads to writes. 4. the operating temperature. 5. the v cc level. 6. i/o loading. real-time clock operation nvtime operation the cy14b101k offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. internal double buffering of the clock and the clock/timer information registers prevents accessing transitional internal clock data during a read or write operatio n. double buffering also circum- vents disrupting normal timing c ounts or clock accuracy of the internal clock while accessing clock data. clock and alarm registers store data in bcd format. clock operations the clock registers maintain time up to 9,999 years in one-second increments. the user can set the time to any calendar time and the clock automatically keeps track of days of the week and month, leap years and century transitions. there are eight registers dedicated to the clock functions which are used to set time wit h a write cycle and to read time during a read cycle. these registers contain the time of day in bcd format. bits defined as ?0? are currently not used and are reserved for future use by cypress. notes: 1. the six consecutive address locations must be in the order listed. we must be high during all six cycles to enable a nonvolatile cycle. 2. while there are 17 address lines on the cy14b101k, only the lower 16 lines are used to control software modes. 3. i/o state depends on the state of oe . the i/o table shown assumes oe low. table 1. mode selection ce we oe a15 - a0 mode i/o power h x x x not selected output high z standby l h l x read sram output data active l l x x write sram input data active l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8b45 read sram read sram read sram read sram read sram autostore disable output data output data output data output data output data output data active [1,2,3] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4b46 read sram read sram read sram read sram read sram autostore enable output data output data output data output data output data output data active [1,2,3] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active i cc2 [1,2,3] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active [1,2,3]
advance information cy14b101k document #: 001-06401 rev. *a page 6 of 23 reading the clock while the double-buffered rtc register structure reduces the chance of reading in correct data from the clock, the user should halt internal updates to the cy14b101k clock registers before reading clock data to prevent the reading of data in transition. stopping the inter nal register updates does not affect clock accuracy. the updating process is stopped by writing a ?1? to the read bit ?r? (in the flags register at 0x1fff0), and will not restart until a ?0? is written to the read bit. the rtc registers can then be read while the internal clock continues to run. within 20 ms af ter a ?0? is written to the read bit, all cy14b101k registers are simultaneously updated. setting the clock setting the write bit ?w? (in the flags register at 0x1fff0) to a ?1? halts updates to the cy14b101k registers. the correct day, date, and time can then be written into the registers in 24-hour bcd format. the time written is referred to as the ?base time.? this value is stored in nonvolatile registers and used in calculation of the current time. resetting the write bit to ?0? transfers those values to the actual clock counters, after which the clock resumes normal operation. backup power the rtc in the cy14b101k is intended for permanently powered operation. either the v rtccap or v rtcbat pin is connected depending on whether a capacitor or battery is chosen for the application. when primary power, v cc , fails and drops below v switch the device will switch to the backup power supply. the clock oscillator uses very little current, which maximizes the backup time available from the backup source. regardless of clock operation with the prim ary source removed, the data stored in nvsram is secure, having been stored in the nonvol- atile elements as power was lost. during backup operation the cy14b101k consumes a maximum of 300 nanoamps at 2 volts. capacitor or battery values should be chosen according to the application. backup time values based on maximum current specs are shown below. nominal times are approximately three times longer. using a capacitor has the obvious advantage of recharging the backup source each time the system is powered up. if a battery is used, a 3v lithium is recommended and the cy14b101k will only source current from the battery when the primary power is removed. the battery will not, however, be recharged at any time by the cy14b101k. the battery capacity should be chosen fo r total anticipated cumulative down-time required over the life of the system. stopping and starting the oscillator the oscen bit in calibration register at 0x1fff8 controls the starting and stopping of the o scillator. this bit is nonvolatile and shipped to customers in the ?enabled? (set to 0) state. to preserve battery life while system is in storage oscen should be set to a 1. this will turn off the oscillator circuit extending the battery life. if the oscen bit goes from disabled to enabled, it will take approximately 5 seconds (10 seconds max) for the oscillator to start. the cy14b101k has the ability to detect oscillator failure. this is recorded in the oscf (oscillator failed bit) of the flags register at address 0x1fff0. when the device is powered on (v cc goes above v switch ) the oscen bit is checked for ?enabled? status. if the oscen bit is enabled and the oscillator is not active, the oscf bit is set. the user should check for this condition and then write a 0 to clear the flag. it should be noted that in addition to setting the oscf flag bit, the time registers are reset to the ?base time? (see the section ?setting the clock?), which is the value la st written to the timekeeping registers. the control/calibration register and the oscen bit are not affected by the o scillator failed condition. if the voltage on the backup supply (either v rtccap or v rtcbat ) falls below their respective minimum level the oscillator may fail, leading to the oscillator failed condition which can be detected when system power is restored. the value of oscf should be reset to 0 when the time registers are written for the firs t time. this will initialize the state of this bit which may have become set when the system was first powered on. calibrating the clock the rtc is driven by a quartz-controlled oscillator with a nominal frequency of 32.768 khz. clock accuracy will depend on the quality of the crystal, usually specified to 35 ppm limits at 25c. this error could equate to +1.53 minutes per month. the cy14b101k employs a calibration circuit that can improve the accuracy to +1/?2 ppm at 25c. the calibration circuit adds or subtracts counts from the oscillator divider circuit. figure 2. current vs. cycle time table 2. rtc backup time capacitor value backup time 0.1f 72 hours 0.47f 14 days 1.0f 30 days
advance information cy14b101k document #: 001-06401 rev. *a page 7 of 23 the number of times pulses are suppressed (subtracted, negative calibration) or spli t (added, positive calibration) depends upon the value loaded into the five calibration bits found in calibration register at 0x1fff8. adding counts speeds the clock up; subtracti ng counts slows the clock down. the calibration bits occupy the five lower-order bits in the control register 8. these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit, where a ?1? indicates positive calibration and a ?0? indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscil- lator cycles. if a binary ?1? is loaded into the register, only the first 2 minutes of the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,82 9,120 actual oscillator cycles. that is 4.068 or ?2.034 ppm of adjustment per calibration step in the calibration register. in order to determine how to set the calibration one may set the cal bit in the flags register at 0x1fff0 to 1, which causes the int pin to toggle at a nominal 512 hz. any deviation measured from the 512 hz will indicate the degree and direction of the required corre ction. for example, a reading of 512.010124 hz would indicate a +20 ppm error, requiring a ?10 (001010) to be loaded into the calibration register. note that setting or changing the calibration register does not affect the frequency test output frequency. alarm the alarm function compares user-programmed values to the corresponding time-of-day values. when a match occurs, the alarm event occurs. the alarm drives an internal flag, af, and may drive the int pin if desired. there are four alarm match fields. they are date, hours, minutes and seconds. each of these fields also has a match bit that is used to determine if the field is used in the alarm match logic. setting the match bit to ?0? indicates that the corresponding field will be used in the match process. depending on the match bits, the alarm can occur as specific- ally as one particular second on one day of the month, or as frequently as once per second continuously. the msb of each alarm register is a match bit. selecting none of the match bits (all 1s) indicates that no match is required. the alarm occurs every second. setting the match select bit for seconds to ?0? causes the logic to match th e seconds alarm value to the current time of day. since a match will occur for only one value per minute, the alarm occurs once per minute. likewise, setting the seconds and minutes match bits causes an exact match of these values. thus, an alarm will occur once per hour. setting seconds, minutes and hours causes a match once per day. lastly, selecting all match values causes an exact time and date match. selecting other bit combinations will not produce meaningful results; however the alarm circuit should follow the functions described. there are two ways a user can detect an alarm event, by reading the af flag or monitoring the int pin. the af flag in the flags register at 0x1fff0 will indicate that a date/time match has occurred. the af bit will be set to 1 when a match occurs. reading the flags/control register clears the alarm flag bit (and all others). a hardware interrupt pin may also be used to detect an alarm event. watchdog timer the watchdog timer is a free running down counter that uses the 32-hz clock (31.25 ms) derived from the crystal oscillator. the oscillator must be running for the watchdog to function. it begins counting down from the value loaded in the watchdog timer register. the counter consists of a loadable register and a free-running counter. on power-up, the watchd og time-out value in register 0x1fff7 is loaded into the counter load register. counting begins on power-up and restarts from the loadable value any time the watchdog strobe (wds) bit is set to 1. the counter is compared to the terminal value of 0. if the counter reaches this value, it causes an internal flag and an optional interrupt output. the user can prevent the time-out interrupt by setting wds bit to 1 prior to the counter reaching 0. this causes the counter to be reloaded with the watchdog time-out value and to be restarted. as long as the user sets the wds bit prior to the counter reaching the terminal value, the interrupt and flag never occurs. new time-out values can be written by setting the watchdog write bit to 0. when the wdw is 0 (from the previous operation), new writes to t he watchdog timeout value bits d5?d0 allow the time-out value to be modified. when wdw is a 1, then writes to bits d 5?d0 will be ignored. the wdw function allows a user to set the wds bit without concern that the watchdog timer value will be modified. a logical diagram of the watchdog timer is shown in figure 3 . note that setting the watchdog time-out value to 0 would be otherwise meaningless and therefore disables the watchdog function. the output of the watchdog timer is a flag bit wdf that is set if the watchdog is allowed to time-out. the flag is set upon a watchdog time-out and cleared when the flags/control register is read by the user. the user can also enable an optional interrupt source to drive the int pin if the watchdog time-out occurs. figure 3. watchdog timer block diagram
advance information cy14b101k document #: 001-06401 rev. *a page 8 of 23 power monitor the cy14b101k provides a power management scheme with power-fail interrupt capability. it also controls the internal switch to backup power for the clock and protects the memory from low-v cc access. the power monitor is based on an internal band-gap reference ci rcuit that compares the v cc voltage to various thresholds. as described in the autostore section previously, when v switch is reached as v cc decays from power loss, a data store operation is initiated from sram to the nonvolatile elements, securing the last sram data state. power is also switched from v cc to the backup supply (battery or capacitor) to operate the rtc oscillator. when operating from the backup source no data may be read or written and the clock functions are not available to the user. the clock continues to operat e in the background. updated clock data is available to the user after t hrecall delay (see autostore/power-up recall) after v cc has been restored to the device. interrupts the cy14b101k provides three potential interrupt sources. they include the watchdog timer, the power monitor, and the clock/calendar alarm. each can be individually enabled and assigned to drive the int pin. in addition, each has an associated flag bit that t he host processor can use to determine the cause of the interrupt. some of the sources have additional control bits that determine functional behavior. in addition, the pin driver has three bits that specify its behavior when an interrupt occurs. the three interrupts each have a source and an enable. both the source and the enable must be active (true high) in order to generate an interrupt output. only one source is necessary to drive the pin. the user can identify the source by reading the flags/control register, whic h contains the flags associated with each source. all flags are cleared to 0 when the register is read. the cycle must be a complete read cycle (we high); otherwise the flags will not be cleared. the power monitor has two programmable settings that are explained in the power monitor section. once an interrupt source is active, the pin driver determines the behavior of the output. it has two programmable settings as shown below. pin driver contro l bits are located in the inter- rupts register. according to the programming selections, the pin can be driven in the backup mode for an alarm interrupt. in addition, the pin can be an active low (open-drain) or an active high (push-pull) driver. if progra mmed for operation during backup mode, it can only be active low. lastly, the pin can provide a one-shot function so that the active condition is a pulse or a level condition. in one-shot mo de, the pulse width is internally fixed at approximately 200 ms. this mode is intended to reset a host microcontroller. in level mode, the pin goes to its active polarity until the flags/control r egister is read by the user. this mode is intended to be used as an interrupt to a host micro- controller. the control bits are summarized as follows: watchdog interrupt enable - wie . when set to 1, the watchdog timer drives the int pin as well as an internal flag when a watchdog time-out occurs. when wie is set to 0, the watchdog timer affects only the internal flag. alarm interrupt enable - aie . when set to 1, the alarm match drives the int pin as well as an internal flag. when set to 0, the alarm match only affects to internal flag. power fail interrupt enable - pfe . when set to 1, the power fail monitor drives the pin as well as an internal flag. when set to 0, the power fail monitor affects only the internal flag. high/low - h/l . when set to a 1, the int pin is active high and the driver mode is push-pull. the int pin can drive high only when v cc > v switch . when set to a 0, the int pin is active low and the drive mode is opendrain. active low (open drain) is operational even in battery backup mode. pulse/level - p/l . when set to a 1 and an interrupt occurs, the int pin is driven for approximately 200 ms. when p/l is set to a 0, the int pin is driven high or low (determined by h/l) until the flags/control register is read. when an enabled interrupt source activates the int pin, an external host can read the flag s/control register to determine the cause. remember that all flags will be cleared when the register is read. if the int pin is programmed for level mode, then the condition will clear and the int pin will return to its inactive state. if the pin is programmed for pulse mode, then reading the flag also will clear the flag and the pin. the pulse will not complete its specified duration if the flags/control register is read. if the int pin is used as a host reset, then the flags/control register should not be read during a reset. during a power-on reset with no battery, the interrupt register is automatically loaded with the value 24h. this causes power-fail interrupt to be enabled with an active-low pulse. figure 4. interrupt block diagram wdf - watchdog timer flag wie - watchdog interrupt pf - power fail flag pfe - power fail enable af - alarm flag aie - alarm interrupt enable p/l - pulse level h/l - high/low enable
advance information cy14b101k document #: 001-06401 rev. *a page 9 of 23 table 3. rtc register map register bcd format data function/range d7 d6 d5 d4 d3 d2 d1 d0 0x1ffff 10s years years years: 00?99 0x1fffe 0 0 0 10s months months months: 01?12 0x1fffd 0 0 10s day of month day of month day of month: 01?31 0x1fffc 0 0 0 0 0 day of week day of week: 01?07 0x1fffb 0 0 10s hours hours hours: 00?23 0x1fffa 0 10s minutes minutes minutes: 00?59 0x1fff9 10s seconds seconds seconds: 00?59 0x1fff8 oscen 0 cal sign calibration calibration values [4] 0x1fff7 wds wdw wdt watchdog [4] 0x1fff6 wie aie pfe abe h/l p/l 0 0 interrupts [4] 0x1fff5 m 0 10s alarm date alarm day alarm, day of month: 01?31 0x1fff4 m 0 10s alarm hours alarm hours alarm, hours: 00?23 0x1fff3 m 10 alarm minutes alarm minutes alarm, minutes: 00?59 0x1fff2 m 10 alarm minutes alarm, seconds alarm, seconds: 00?59 0x1fff1 10s centuries centuries centuries: 00?99 0x1fff0 wdf af pf oscf 0 cal w r flags [4] note: 4. is a binary value, not a bcd value.
advance information cy14b101k document #: 001-06401 rev. *a page 10 of 23 table 4. register map detail 0x1ffff time keeping - years d7 d6 d5 d4 d3 d2 d1 d0 10s years years contains the lower two bcd digits of the year. lower nibble contains the value for years; upper nibble contains the value for 10s of years. each nibble operates from 0 to 9. the range for the register is 0?99. 0x1fffe time keeping - months d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 10s month months contains the bcd digits of the month. lower nibble contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates fr om 0 to 1. the range for the register is 1?12. 0x1fffd time keeping - date d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s day of month day of month contains the bcd digits for the date of the month. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3. the range fo r the register is 1?31. leap years are automatically adjusted for. 0x1fffc time keeping - day d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 day of week lower nibble contains a value that correlates to day of the week. day of the week is a ri ng counter that counts from 1 to 7 then returns to 1. the user must assign meaning to the day value, as the day is not integrated with the date. 0x1fffb time keeping - hours d7 d6 d5 d4 d3 d2 d1 d0 12/24 0 10s hours hours contains the bcd value of hours in 24 hour format. lower nibble contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. the range for the register is 0?23. 0x1fffa time keeping - minutes d7 d6 d5 d4 d3 d2 d1 d0 0 10s minutes minutes contains the bcd value of minutes. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper minutes digit and operates from 0 to 5. the range for the register is 0?59. 0x1fff9 time keeping - seconds d7 d6 d5 d4 d3 d2 d1 d0 0 10s seconds seconds contains the bcd value of seconds. lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 5. the range for the register is 0?59. 0x1fff8 calibration/control d7 d6 d5 d4 d3 d2 d1 d0 oscen 0 calibration sign calibration oscen oscillator enable. when set to 1, the oscillator is halted. when set to 0, the oscillator runs. disabling the oscillator saves battery/capacitor power during storage. on a no-battery power-up, this bit is set to 0. calibration sign determines if the calibration adjustment is applied as an addition to or as a subtraction from the time-base. calibration these five bits control the calibration of the clock.
advance information cy14b101k document #: 001-06401 rev. *a page 11 of 23 0x1fff7 watchdog timer d7 d6 d5 d4 d3 d2 d1 d0 wds wdw wdt wds watchdog strobe. setting this bit to 1 reloads and restar ts the watchdog timer. setting the bit to 0 has no affect. the bit is cleared automatically once the watchdog timer is reset. the wds bit is write only. reading it always will return a 0. wdw watchdog write enable. setting this bit to 1 masks th e watchdog time-out value (wdt5?wdt0) so it cannot be written. this allows the user to strobe the watchdog without disturbing the time-out value. setting this bit to 0 allows bits 5?0 to be written on the next write to the watchdog register. the new value will be loaded on the next internal watchdog clock after the write cycle is complete. this fu nction is explained in more detail in the watchdog timer section. wdt watchdog time-out selection. the watchdog timer interval is selected by the 6-bit value in this register. it represents a multiplier of the 32-hz count (31.25 ms). the minimum ra nge or time-out value is 31.25 ms (a setting of 1) and the maximum time-out is 2 seconds (setting of 3fh). setting the watchdog timer register to 0 disables the timer. these bits can be writ ten only if the wdw bit was cleared to 0 on a previous cycle. 0x1fff6 interrupt status/control d7 d6 d5 d4 d3 d2 d1 d0 wie aie pfie abe h/l p/l 00 wie watchdog interrupt enable. when set to 1 and a watchdog time-out occurs, the watchdog timer drives the int pin as well as the wdf flag. when set to 0, t he watchdog time-out affects only the wdf flag. aie alarm interrupt enable. when set to 1, the alarm match dr ives the int pin as well as the af flag. when set to 0, the alarm match only affects the af flag. pfie power-fail enable. when set to 1, the alarm match drives the int pin as well as the af flag. when set to 0, the power-fail monitor affects only the pf flag. abe alarm battery-backup enable. when set to 1, the alarm interr upt (as controlled by aie) will function even in battery backup mode. when set to 0, the alarm will occur only when v cc > v switch . h/l high/low. when set to a 1, the int pin is driven active high. when set to 0, the int pin is open drain, active low. p/l pulse/level. when set to a 1, the int pin is driven acti ve (determined by h/l) by an interrupt source for approxi- mately 200 ms. when set to a 0, the int pin is driven to an active level (as set by h/l) until the flags/control register is read. 0x1fff5 alarm - day d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm date alarm date contains the alarm value for the date of the month and the mask bit to select or deselect the date value. m match. setting this bit to 0 causes the date value to be used in the alarm match. setting this bit to 1 causes the match circuit to ignore the date value. 0x1fff4 alarm - hours d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm hours alarm hours contains the alarm value for the hours and the mask bit to select or deselect the hours value. m match. setting this bit to 0 causes the hours value to be us ed in the alarm match. setting this bit to 1 causes the match circuit to ignore the hours value. 0x1fff3 alarm - minutes d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm minutes alarm minutes contains the alarm value for the minutes and the ma sk bit to select or deselect the minutes value. m match. setting this bit to 0 causes the minutes value to be used in the alarm match. setting this bit to 1 causes the match circuit to ignore the minutes value. table 4. register map detail (continued)
advance information cy14b101k document #: 001-06401 rev. *a page 12 of 23 0x1fff2 alarm - seconds d7 d6 d5 d4 d3 d2 d1 d0 m 0 10s alarm seconds alarm seconds contains the alarm value for the seconds and the mask bit to select or deselect the seconds? value. m match. setting this bit to 0 causes the seconds? value to be used in the alar m match. setting this bit to 1 causes the match circuit to ignore the seconds value. 0x1fff1 time keeping - centuries d7 d6 d5 d4 d3 d2 d1 d0 0 0 10s centuries centuries 0x1fff0 flags d7 d6 d5 d4 d3 d2 d1 d0 wdf af pf oscf 0 cal w r wdf watchdog timer flag. this read-only bit is set to 1 wh en the watchdog timer is allowed to reach 0 without being reset by the user. it is cleared to 0 when the flags/control register is read. af alarm flag. this read-only bit is set to 1 when the time an d date match the values stored in the alarm registers with the match bits = 0. it is cleared wh en the flags/control register is read. pf power-fail flag. this read-only bit is set to 1 when power falls below the power-fail threshold v switch . it is cleared to 0 when the flags/control register is read. oscf oscillator fail flag. set to 1 on power-up only if the osci llator is not running in the first 5 ms of power-on operation. this indicates that time counts are no longer valid. the user must reset this bit to 0 to clear this condition. the chip will not clear this flag. this bit survives power cycles. cal calibration mode. when set to 1, a 512-hz square wave is ou tput on the int pin. when set to 0, the int pin resumes normal operation. this bit defaults to 0 (disabled) on power-up. w write time. setting the w bit to 1 fr eeze updates of the timekeeping register s. the user can then write them with updated values. setting the w bit to 0 causes the contents of the time registers to be transferred to the timekeeping counters. r read time. setting the r bit to 1 copies a static image of the timekeeping registers and places them in a holding register. the user can then read them without concerns over changing values causing system errors. the r bit going from 0 to 1 causes the timekeeping capture, so th e bit must be returned to 0 prior to reading again. table 4. register map detail (continued)
advance information cy14b101k document #: 001-06401 rev. *a page 13 of 23 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc relative to gnd.......... ?0.5v to 4.1v voltage applied to outputs in high-z state .......................................?0.5v to v cc + 0.5v input voltage ............................................ ?0.5v to vcc+0.5v transient voltage (<20 ns) on any pin to ground potential...................?2.0v to v cc + 2.0v package power dissipation capability (t a = 25c) ................................................... 1.0w surface mount lead soldering temperature (3 seconds) .......................................... +240 c output short circuit current [5] ..................................... 15 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma table 5. operating range range ambient temperature v cc commercial 0 c to +70 c 2.7v to 3.6v industrial ?40 c to +85 c 2.7v to 3.6v shaded area contains advance information dc electrical characteristics over the operating range (v cc = 2.7v to 3.6v) [6] parameter description test conditions min. max. unit i cc1 average v cc current t rc = 25 ns t rc = 35 ns t rc = 45 ns dependent on output loading and cycle rate. values obtained without output loads. i out = 0ma. commercial 65 55 50 ma ma ma industrial 70 60 55 ma ma ma i cc2 average v cc current during store all inputs don?t care, v cc = max. average current for duration t store 3ma i cc3 average v cc current at t avav = 200 ns, 3v, 25c typical we > (v cc ? 0.2). all other inputs cycling. dependent on output loading and cycle rate. values obtained without output loads. 5ma i cc4 average v cap current during autostore cycle all inputs don?t care, v cc = max. average current for duration t store 3ma i sb v cc standby current we > (v cc ? 0.2). all others v in < 0.2v or > (v cc ? 0.2v). standby current level after n onvolatile cycle is complete. inputs are static. f = 0mhz 2ma i ix input leakage current v cc = max., v ss < v in < v cc -1 +1 a i oz off-state output leakage current v cc = max., v ss < v in < v cc , ce or oe > v ih -1 +1 a v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage i out = ?2 ma 2.4 v v ol output low voltage i out = 4 ma 0.4 v v cap storage capacitor between v cap pin and v ss , 5v rated 17 57 f table 6. capacitance [7] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 0 to 3.0v 7pf c out output capacitance 7 pf notes: 5. outputs shorted for no more than one second. no more than one output shorted at a time. 6. typical conditions for the active current shown on the front page of the data sheet are average values at 25c (room temperat ure), and v cc = 3v. not 100% tested. 7. these parameters are guaranteed but not tested.
advance information cy14b101k document #: 001-06401 rev. *a page 14 of 23 table 7. thermal resistance [7] parameter description test conditions 48-ssop unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. tbd c/w jc thermal resistance (junction to case) tbd c/w ac test loads ac test conditions 3.0v output 5 pf r1 577 ? r2 789 ? 3.0v output 30 pf r1 577 ? r2 789 ? for tri-state specs input pulse levels.......................................... 0v to 3v input rise and fall times (10% - 90%)............... < 5ns input and output timing reference levels...........1.5v
advance information cy14b101k document #: 001-06401 rev. *a page 15 of 23 table 8. ac switching characteristics parameters description cy14b101k-25 cy14b101k-35 cy14b101k-45 unit min. max. min. max. min. max. cypress parameter alt. parameter sram read cycle t ace t acs chip enable access time 25 35 45 ns t rc [8] t rc read cycle time 25 35 45 ns t aa [9] t aa address access time 25 35 45 ns t doe t oe output enable to data valid 12 15 20 ns t oha [9] t oh output hold after address change 3 3 3 ns t lzce [10] t lz chip enable to output active 3 3 3 ns t hzce [10] t hz chip disable to output inactive 10 13 15 ns t lzoe [10] t olz output enable to output active 0 0 0 ns t hzoe [10] t ohz output disable to output inactive 10 13 15 ns t pu [7] t pa chip enable to power active 0 0 0 ns t pd [7] t ps chip disable to power standby 25 35 45 ns sram write cycle t wc t wc write cycle time 25 35 45 ns t pwe t wp write pulse width 20 25 30 ns t sce t cw chip enable to end of write 20 25 30 ns t sd t dw data set-up to end of write 10 12 15 ns t hd t dh data hold after end of write 0 0 0 ns t aw t aw address set-up to end of write 20 25 30 ns t sa t as address set-up to start of write 0 0 0 ns t ha t wr address hold after end of write 0 0 0 ns t hzwe [10,11] t wz write enable to output disable 10 13 15 ns t lzwe [10] t ow output active after end of write 3 3 3 ns notes: 8. we must be high during sram read cycles. 9. device is continuously selected with ce and oe both low. 10. measured 200mv from steady state output voltage. 11. if we is low when ce goes low,the outputs remain in the high impedance state
advance information cy14b101k document #: 001-06401 rev. *a page 16 of 23 table 9. autostore/power-up recall parameters description cy14b101k units t hrecall [12] power-up recall duration 20 ms t store [13] store cycle duration 12.5 ms v switch low voltage trigger level 2.55 2.65 v t vccrise vcc rise time 150 s table 10.software controlled store/recall cycle [14,15] parameters description cy14b101k-25 cy14b101k-35 cy14b101k-45 units min. max. min. max. min. max. t rc store/recall initiation cycle time 25 35 45 ns t as address set-up time 0 0 0 ns t cw clock pulse width 20 25 30 ns t glax address hold time 20 20 20 ns t recall recall duration 40 40 40 s table 11.hardware store cycle parameters description cy14b101k units min max t delay [16] time allowed to complete sram cycle 1 s t hlhx hardware store pulse width 15 ns t hlbl hardware store low to store busy 300 ns switching waveforms figure 5. sram read cy cle #1: address controlled [8,9,17] notes: 12. t hrecall starts from the time v cc rises above v switch . 13. if an sram write has not taken place since the last nonvolatile cycle, no store will take place. 14. the software sequence is clocked with ce controlled or oe controlled reads. 15. the six consecutive addr esses must be read in the order listed in the mode selection table. we must be high during a ll six consecutive cycles. 16. read and write cycles in progress before hsb are given this amount of time to complete. 17. hsb must remain high during read and write cycles. t rc t aa t oh
advance information cy14b101k document #: 001-06401 rev. *a page 17 of 23 figure 6. sram read cycle #2: ce and oe controlled [8,17] figure 7. sram write cycle #1: we controlled [17,18] note: 18. ce or we must be > v ih during address transitions. switching waveforms (continued) ce oe t ace t lzce t pu t hzce t doe t lzoe t hzoe t pu ce we t sce t ha t sa t pwe t sd t hd t hzwe t lzwe
advance information cy14b101k document #: 001-06401 rev. *a page 18 of 23 figure 8. sram write cycle #2: ce controlled figure 9. autostor e/power-up recall switching waveforms (continued) ce we t sa t sce t ha t pwe t sd t hd
advance information cy14b101k document #: 001-06401 rev. *a page 19 of 23 figure 10. ce -controlled software store/recall cycle [15] figure 11. oe -controlled software store/recall cycle [15] switching waveforms (continued) t glax ce oe t sa t sce ce oe t sa t sce
advance information cy14b101k document #: 001-06401 rev. *a page 20 of 23 figure 12. hardware store cycle switching waveforms (continued)
advance information cy14b101k document #: 001-06401 rev. *a page 21 of 23 ordering information speed (ns) ordering code package diagram package type operating range 25 cy14b101k-sp25ct 51-85061 48-pin ssop pb-free commercial CY14B101K-SP25It 51-85061 48-pin ssop pb-free industrial CY14B101K-SP25I 51-85061 48-pin ssop pb-free 45 cy14b101k-sp45ct 51-85061 48-pin ssop pb-free commercial cy14b101k-sp45it 51-85061 48-pin ssop pb-free industrial cy14b101k-sp45i 51-85061 48-pin ssop pb-free shaded areas contain advance information. plea se contact your local cypress sales repr esentative for availability of these part s. option: t - tape & reel blank - std. temperature: c - commercial (0 to 70c) i - industrial (?40 to 85c) a - automotive (?40 to 125c) speed: 25 - 25 ns 35 - 35 ns 45 - 45 ns 55 - 55 ns data bus: k - x8 + rtc l - x8 density: 016 - 16 kb 064 - 64 kb 256 - 256 kb 101 - 1 mb 102 - 2 mb 104 - 4 mb voltage: a - 1.8v b - 3.0v c - 3.3v cypress part numbering nomenclature cy 14 b 101 k - sp 25 c t d - 3.0/3.3v e - 5.0v nvsram 14 - autostore + software store + hardware store 11 - software store 15 - autostore + software store 16 - autostoreplus + hardware store 10 - hardware store 22 - autostore + hardware store 25 - autostore package: sp - 48 ssop
advance information cy14b101k document #: 001-06401 rev. *a page 22 of 23 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. autostore and quantumtrap are registered trademar ks of simtek corporation.all produc ts and company names mentioned in this document are the trademarks of their respective holders. package diagrams 48-lead shrunk small outline package (51-85061) 51-85061-*c
advance information cy14b101k document #: 001-06401 rev. *a page 23 of 23 document history page document title: cy14b101k 1-mbit (128 k x 8) nvsram with real-time clock document number: 001-06401 rev. ecn no. issue date orig. of change description of change ** 425138 see ecn tup new data sheet *a 437321 see ecn tup show data sheet on external web

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